This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-024872, filed Feb. 2, 2000; and No. 2000-027040, filed Feb. 4, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a connection structure of a display device on which a plurality of IC chips are mounted by, for example, the COG (Chip On Glass) method and a wiring board.
FIG. 9 is a plan view of a conventional liquid crystal display unit. The liquid crystal display unit includes an active matrix type liquid crystal panel 1. The liquid crystal display panel 1 is such that a lower glass substrate 2 and an upper glass substrate 3 are overlapped together with seal material (not shown) therebetween, with liquid crystal (not shown) sealed between the substrates. The display panel 1 has a display area inside the area represented by a two-dots-dash line and an undisplayed area outside the two-dots-dash line area. In this case, the lower glass substrate 2 has a larger area than that of the upper glass substrate 3 and includes a lower edge section 2a projecting from below the lower end (in the figure) of the upper glass substrate 3 and a right edge section 2b projecting from the right end of the substrate 3.
On the lower edge section 2a of the lower glass substrate 2, three semiconductor chip mounting areas 21A, 21B, and 21C are arranged in series. In each of the semiconductor chip mounting areas 21A, 21B, 21C, a semiconductor chip 4 for supplying a data signal is mounted on the lower edge section 2a with anisotropic conductive adhesive (not shown) by the COG (Chip On Glass) method. On the right edge section 2b of the lower glass substrate 2, there is provided a semiconductor chip mounting area 21E, on which a semiconductor chip 5 for supplying a scanning signal is mounted via anisotropic conductive adhesive (now shown).
Although not shown, a plurality of scanning lines extending in the direction of row (or in the horizontal direction in FIG. 9) and a plurality of signal lines extending in the direction of column (or in the vertical direction in FIG. 9) are provided in the area of the lower glass substrate 2 corresponding to the display area 6 enclosed by the two-dots-dash line. The right ends of the scanning lines are connected via output wires 7 provided on the top surface of the lower glass substrate 2 to the semiconductor chip 5 mounted on the right edge section 2b. This connection enables the semiconductor chip 5 to supply scanning line driving signals to the plurality of scanning lines. The lower ends of the signal lines are connected to the corresponding semiconductor chips 4 via output wires 8 provided on the top surface of the lower glass substrate 2. With this connection, the three semiconductor chips 4 mounted on the lower edge section 2b supply signal line driving signals to the individual signal lines.
In the vicinity of the outside of the semiconductor chip mounting areas 21A, 21B, 21C, one end of a flexible wiring board 11 is mounted on the lower edge section 2a of the lower glass substrate 2. The flexible wiring board 11 and the semiconductor chips 4 are electrically connected to input wire groups 12 provided in three places, one group in one place, on the lower edge section 2a of the lower glass substrate 2 via anisotropic conductive adhesive (not shown). The flexible wiring board 11 and the semiconductor chip 5 on the right edge section 2b are electrically connected via an input wiring group 13 provided on the right edge section 2b of the lower glass substrate 2 and its peripheral section.
FIG. 10A is an enlarged plan view of the vicinity of the semiconductor chip mounting areas 21A, 21B, 21C of the lower edge section 2a of the liquid crystal display panel 1 shown in FIG. 9. Since the inside of each of the semiconductor chip mounting areas 21A, 21B, 21C and its vicinity have the same configuration, the vicinity of the semiconductor chip mounting area 21B positioned in the middle is taken as an example. In FIG. 10A, the semiconductor chip 4 mounted on the semiconductor chip mounting area 21B is not shown. The area enclosed by a one-dot-dash line on the top surface of the lower edge section 2a of the lower glass substrate 2 is the semiconductor chip mounting area 21B on which a semiconductor chip 4 is mounted. The input wiring group 12 is composed of a plurality of narrow signal input wires 14 and five wide power supply wires 15. In this case, the signal input wires 14 and power supply wires 15 are arranged according to the specification of the semiconductor chip 4 (or the location of a signal input bump electrode and a power supply bump electrode) explained later.
Each of the signal input wires 14 and power supply wires 15 is extended straightly from the inside of the semiconductor chip mounting area 21B up to the vicinity of the side end of the lower glass substrate 2. Each signal input wire 14 has an electrode terminal 14a located at the lower edge section inside the semiconductor chip mounting area 21B and a terminal 14b near the side end of the lower glass substrate 2. Each power supply wire 15 has an electrode terminal 15a located at the lower edge section inside the semiconductor chip mounting area 21B and a terminal 15b near the side end of the lower glass substrate 2.
The signal input wires 14 and power supply wires 15 are made of transparent metal, such as ITO (Indium Tin Oxide). The reason why the power supply wire 15 is made wider than the signal input wire 14 is to reduce the wire resistance, because a larger current flows through the power supply wire 15 than through the signal input wire 14. The input wire group 13, whose detailed view is not given, is composed of a plurality of power supply wires and control signal input wires for connecting the flexible wiring board 11 with the semiconductor chip 5.
As shown in FIG. 9, the flexible wiring board 11 is provided with a film 22 having a wide section 22a and a narrow section 22b extended from almost the middle of the lower part of the wide section 22a. On the bottom surface of the wide section 22a of the film 22, three connection wire groups 23 corresponding to the respective three input wire groups are formed. The middle connection wire group is shown in a transparent enlarged plan view of FIG. 10B (or an enlarged plan view of the central portion with the film 22 removed from above as in FIG. 10A). Each connection wire group 23 corresponds to each input wire group 12 and is composed of a plurality of narrow input connection wires 24 corresponding to the signal input wires 14 and five wide power supply connection wires 25 corresponding to the power supply wires 15. Each input connection wire 24 has a connection terminal 24a connected to the terminal 14b of the corresponding signal input wire 15 at its upper end. Each power supply connection wire 25 has a connection terminal 25a connected to the power supply terminal 15b of the corresponding power supply wire 15 at its upper end.
A plurality of input connection wires 24 and five power supply connection wires 25 constituting the middle connection wire group 23 formed at the wide section of the flexible wiring board 11 are extended to the lower end edge of the narrow section 22b of the film 22 and connected to a circuit board (not shown). On the other hand, input connection wires 24 and power supply connection wires 25 constituting the remaining two connection wire groups 23 are connected to the corresponding input connection wires 24 or power supply connection wires 25 of the middle connection wire groups 23 via running wires so formed through holes and on the top surface of film 22 that they traverse the input connection wires 24 and power supply connection wires 25.
Specifically, the flexible wiring board 11 is a double-sided wiring board where the three connection wire groups 23 are formed on the bottom surface of the film 22, each group composed of a plurality of input connection wires 24 and five power supply connection wires 25, and the running wires 22 formed on the top surface of the film 22 and connecting the input connection wires 24 and power supply connection wires 25 of the middle connection wire group 23 with the input connection wires 24 and power supply connection wires 25 of the right and left connection wire groups 23, respectively. The three connection wire groups 23 are provided in parallel on the bottom surface of the wide section 22a of the film 22. Of the three groups, only the middle connection wire group 23 is extended to the lower end edge of the narrow section 22b of the film 22.
FIG. 11A is a transparent enlarged plan view to show the location of the terminals of the semiconductor chip 4 mounted on the semiconductor chip mounting area 21B of the liquid crystal display panel 1 of FIG. 11A (or an enlarged plan view showing only the terminal with the semiconductor body removed from above). FIG. 11B is an enlarged view of the semiconductor chip mounting area 21B of the liquid crystal display panel 1 shown in FIG. 10A. At the upper edge section inside the semiconductor chip mounting area 21B of the liquid crystal display panel 1, output electrode terminals 8a composed of one-end parts of a plurality of output wires 8 are provided in staggered fashion. At the lower edge section of the bottom surface of the semiconductor chip 4, a plurality of signal input bump electrodes 31 and five pairs of power supply pump electrodes 32 (two pairs are shown in FIG. 11A) are provided. At the upper edge section of the bottom surface, a plurality of output bump electrodes 33 are provided in staggered fashion. In the description, the power supply bump electrodes 32 are connected pair by pair inside the semiconductor chip 4, each pair corresponding to each electrode terminal 15a. 
Then, with the semiconductor chips 4 bonded to the respective semiconductor chip mounting areas 21A to 21C of the liquid crystal display panel 1 using anisotropic conductive adhesive, the signal input bump electrodes 31, power supply bump electrodes 32, and output bump electrode 33 of the semiconductor chips 4 are connected to the electrode terminals 14a, 15a and output electrode terminals 8a inside each of the semiconductor chip mounting area 21A to 21C of the liquid crystal panel 1.
As shown in FIG. 9 and FIG. 10B, in the flexible wiring board 11 of such a conventional liquid crystal display unit, three connection wire groups 23 are provided in parallel on the bottom surface of the wide section 22a of the film 22, each group being composed of a plurality of input connection wires 24 and five power supply connection wires 25. Of the three groups, a plurality of input connection wires 24 and five power supply wires 25 constituting the two connection wire groups 23 on both sides are connected to a plurality of input connection wires 24 and five power supply connection wires 25 constituting the middle connection wire group 23 and the common running wires provided on the top surface of the wide section 22a of the film 22. As a result, the lateral length (the dimension in the vertical direction in FIG. 9) of the wide section 22a of the film 22 becomes larger, increasing the overall occupied area and therefore decreasing the number of films obtained from a base film of a constant area, which leads to a high cost problem.
The object of the present invention is to decrease the occupied area of a flexible wiring board.
According to the present invention, there is provided a connection structure of a display panel and a wiring board, comprising: a display panel which has a display area and is composed of a plurality of semiconductor chip mounting areas, output wires that are formed so as to correspond to the semiconductor chip mounting areas respectively and supply driving signals to the display area, first and second input wires. Each of the first input wires having an electrode terminal located inside the semiconductor chip mounting area and an input terminal located outside the semiconductor chip mounting area, and the second input wires having junction sections for connecting electrode terminals respectively located inside adjacent ones, the semiconductor chip mounting area with each other, and input terminals arranged near outside the one located at one end of the semiconductor chip mounting areas; and
a wiring board including connection wires connected to the input terminals of the first input wires arranged so as to correspond to the plurality of semiconductor chip mounting areas respectively and connection wires connected to the input terminals of the second input wires.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.